Reference is made to FIG. 1 which shows a schematic diagram of a standard six transistor (6T) static random access memory (SRAM) cell 10. The cell 10 includes two cross-coupled complement metal-oxide-semiconductor (CMOS) inverters, each inverter including a series connected p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) transistor pair. A first inverter includes a PMOS transistor 12 and an NMOS transistor 14, and a second inverter includes a PMOS transistor 16 and an NMOS transistor 18. The inputs and outputs of the inverters are coupled to form a latch circuit having a true data storage (DST) node and a complement data storage (DSC) node. The cell 10 further includes two access transistors (sometimes referred to as passgate or transfer transistors) 24 and 26 whose gate terminals are coupled with a wordline node and are controlled by the signal present at the wordline node (WL). The transistor 24 is source-drain connected between the DST node and a node associated with a true bitline (BLT). The transistor 26 is source-drain connected between the DSC node and a node associated with a complement bitline (BLC). The source terminals of the PMOS transistors 12 and 16 in each inverter are coupled to receive a high supply voltage (for example, VDD) at a high voltage node VH, while the source terminals of the NMOS transistors 14 and 18 are coupled to receive a low reference voltage (for example, ground) at a low voltage node VL. The high supply voltage VDD at the node VH and the low reference voltage ground at the node VL comprise the power supply set of voltages for the cell 10.
The reference above to a 6T SRAM cell 10 of FIG. 1 for use as the data storage element is made by way of example only, it being understood to those skilled in the art that the cell 10 could alternatively comprise a different data storage element. The use of the term SRAM cell will accordingly be understood to refer any suitable memory cell or date storage element, with the circuitry, functionality, and operations presented herein in the exemplary context of a 6T SRAM cell.